The present invention relates to the field of semiconductor integrated circuits. More specifically, the present invention relates to a method and apparatus for reducing leakage current and improving power consumption for n-type channel metal oxide semiconductor (NMOS) and p-type channel metal oxide semiconductor (PMOS) transistors.
Power consumption is an issue for advanced integrated circuit parts such as transistors. Tunneling leakage current (gate leakage) and standby leakage current (source drain leakage) contribute to the power consumption problem.
One approach used in the past to address tunneling leakage currents in transistors was to fabricate the transistors with a thicker gate dielectric. This approach, however, had several drawbacks. First, fabricating a transistor with a thicker gate dielectric involved multiple gate oxidations. This required additional time and resources for implementing additional processes during manufacturing which was undesirable. Second, although fabricating the transistor with a thicker gate dielectric reduced the tunneling leakage current when the transistor was in an ON state, the approach did not address the standby leakage current when the transistor was in an OFF state. On the contrary, fabricating the transistor with a thicker gate dielectric increased the amount of standby leakage current generated between the source and drain which was undesirable. Thus, what is needed is an efficient and effective approach to addressing both tunneling leakage current and standby leakage current.
A method for fabricating transistors on a semiconductor substrate which addresses both tunneling leakage current and standby leakage current is disclosed. By reducing the polysilicon doping level of the transistor, the polysilicon depletion region of the transistor is increased when the transistor is in an ON state. This has the effect of allowing a transistor with a relatively thin physical gate dielectric to behave as if having a relatively thick effective gate dielectric when in the ON state. By varying the polysilicon doping level of transistors on the semiconductor substrate, the method of the present invention allows fabrication of transistors having varying effective gate dielectric thickness without physically varying the actual gate dielectric thickness of the transistors. This reduces the number of complex dielectric production steps that may be needed for the fabrication of transistors on a semiconductor substrate.
A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.
A method for fabricating transistors on a semiconductor substrate is disclosed according to a second embodiment of the invention. A polysilicon region of a first transistor on the semiconductor substrate is blocked while a polysilicon region of a second transistor on the semiconductor substrate is exposed. Exposed regions are doped with charges.
A method for fabricating transistors on a semiconductor substrate is disclosed according to a third embodiment of the present invention. A gate, source, and drain is formed for each of a first and second transistor on the semiconductor substrate. A polysilicon region that defines the gate of the second transistor is blocked while a polysilicon region that defines the gate of the first transistor is exposed. Exposed regions are counter doped with charges.
A method for fabricating a transistor on a semiconductor substrate is disclosed according to an embodiment of the present invention. A polysilicon doping level near a first and second edge of a diffusion region is varied with a polysilicon doping level of a center region of a polysilicon region.
A semiconductor substrate is disclosed according to an embodiment of the present invention. The semiconductor substrate includes a first transistor having a gate dielectric of a first thickness and a gate with a first level of polysilicon doping. The semiconductor substrate includes a second transistor having a gate dielectric of the first thickness and a gate with a second level of polysilicon doping.